The present disclosure relates generally to gallium nitride (GaN) heterojunction field effect transistors (HFETs) and, more particularly, to a driver circuit and integrated circuit implementation of a driver circuit for GaN HFETs.
Research on wide-band III-Nitride semiconductor materials, such as GaN, has been rapidly developing in the past few years. These materials have unique properties, including high electron mobility, high saturation velocity, high sheet-carrier concentration at heterojunction interfaces, high breakdown voltages, low thermal impedance (when grown over SiC or bulk AlN substrates), chemical inertness, and radiation hardness.
Compared with Si FETs, GaN HFETs have lower specific on-resistance due to the high-density, two-dimensional electron gas, and high electron mobility. For instance, the on-resistance of GaN HFETs is almost three orders lower than that of Si MOSFETs. In addition, GaN HFETs can work at relatively high temperature ranges which Si MOSFETs cannot reach and have higher breakdown fields than Si MOSFETs due to the large bandgap energy of GaN material. III-Nitride transistors have been shown to operate at up to 300° C. with no noticeable parameter degradation. III-Nitride transistors also have high breakdown voltages of up to, for instance, 1600V. Furthermore, the switching speeds of GaN HFETs are expected to be higher than those of Si MOSFETs due to low gate-source capacitance.
Both the relatively low gate-source capacitance and relatively low on-resistance of GaN HFETs provide for good switching characteristics. For instance, when applied to power electronics, the GaN HFETs allow for high power switching with sub-microsecond and nanosecond switching times. These properties make III-Nitride technology a promising approach for high-power, high-temperature, high-speed, and high-efficiency applications. Using insulated gate III-Nitride HFETs further increases achievable power levels and further improves high temperature stability. Because of the above characteristics, GaN HFETs would be extremely useful in industrial power electronic applications and would improve efficiency and regulation in, for instance, AC-DC and DC-DC power converters, DC-AC inverters, and other power electronic devices.
Currently, however, driver circuits for GaN HFET switches are not commercially available. The lack of available high-frequency driver circuits is one factor preventing the application of GaN HFETs in power electronic devices. Modified driver integrated circuits for power Si MOSFETs can be used to drive GaN HFET switches. Unfortunately, however, most modified driver circuits for power Si MOSFETs work at low frequencies, such as below 1 MHz. A few driver circuits are known to work at about 5 MHz, but the output impedance of these driver circuits is not compatible with GaN HFET devices and can lead to unnecessary power loss.
Conventional driver circuits typically include a pair of complementary devices, such as a pair of emitter followers in an AB class amplifier or PMOS and NMOS transistors in a totem pole configuration. These devices supply the charge needed to charge the gate-source capacitance of the power transistor to allow the transistor to turn on and off (i.e. switch between a conducting state and a non-conducting state). These approaches are well-suited for low frequency applications. However, when the frequency increases, neither the losses due to switching the driver circuit MOSFETs or the power transistor are acceptable.
Driver circuits capable of operating at high frequencies exist. Among these approaches, one of the most efficient is the resonant gate drive circuit. In a resonant gate drive circuit, switching loss reduction, critical in high frequency applications, is obtained by resonant transitions in an LC circuit that involves the gate-source capacitance of the power transistor.
FIG. 1 illustrates an exemplary resonant drive circuit 100 with efficient energy recovery capabilities and FIG. 2 depicts its relevant wave forms. The principle of operation of the resonant drive circuit 100 is that energy stored in the gate-source capacitance Ciss for power transistor 120 is recycled and stored back in the gate-source capacitance Ciss, but with the opposite voltage polarity. Thus, energy is always stored in the gate-source capacitance Ciss, but the effective gate-source capacitor voltage is alternated between a positive voltage state and a negative voltage state. In this manner, a quasi square wave voltage can be imposed on gate-source capacitance Ciss in a low-loss manner. The process is achieved when the inductor LR and capacitance Ciss are resonating together, with resonance being stopped when the gate-source capacitance Ciss is at a minimum or at a maximum
With reference to FIGS. 1 and 2, the operation of the exemplary resonant drive circuit 100 will now be discussed beginning at the negative storage position when the gate-source voltage Vgs_M1 of power transistor 120 is approximately zero and when both PMOS transistor 102 and NMOS transistor 104 are turned off (i.e. are in a non-conducting state). At time t1, when PMOS transistor 102 is turned on, the inductor current iLR begins to flow and charges the gate-source capacitor Ciss of the power transistor 120. When the voltage across the gate-source capacitor Ciss reaches a value slightly higher than VDD at t2, the diode 110 conducts and clamps the gate-source voltage Vgs_M1 at VDD and the inductor current iLR continues to flow freewheeling along diode 110. At time t3, PMOS transistor 102 turns off causing the inductor current iLR to decrease. This causes the diode 108 to conduct and the inductor current iLR to flow from GND to VDD by way of diode 108, inductor LR, and diode 110, thereby returning energy to the voltage source VDD. Between t3 and t4, the inductor current iLR decreases from IPEAK to zero and the gate source voltage Vgs_M1 remains at VDD.
At time t5, the NMOS transistor 104 turns on and the inductor current iLR begins to flow in the opposite direction, discharging the gate-source capacitance Ciss of the power transistor 120 until the voltage across gate-source capacitance Ciss is slightly less than zero at t6. The diode 112 then conducts and clamps the gate-source voltage Vgs_M1 of power transistor 120 at zero as the inductor current iLR continues to flow freewheeling along diode 112. At time t7, when NMOS transistor 104 turns off, the inductor current increases, causing the diode 106 to conduct. The inductor current iLR then flows from GND to VDD by way of diode 112, inductor LR and diode 106, returning energy to the voltage source VDD. Between t7 and t8, the inductor current iLR increases from −IPEAK to zero and the gate-source voltage Vgs_M1 of the power transistor 120 remains at GND.
By using the LC resonant circuit topology discussed above and the two clamp diodes 110 and 112, the power losses of the driving circuit 100 can be reduced. Indeed, the smaller the gate resistance of power transistor 120, the smaller the power loss of the driver circuit 100. In addition, energy used for commutation can be recovered.
While the high efficiency drive circuit 100 of FIG. 1 is a suitable driver circuit for high-frequency applications and has the property of voltage clamping required for driving GaN HFETs, the resonant drive circuit 100 of FIG. 1 is not directly applicable to GaN HFET devices. For instance, GaN HFETs are zero voltage turn-on devices. In particular, GaN HFETs require a zero voltage to turn on (i.e. to be in a conducting state) and a negative voltage to turn off (i.e. to be in a non-conducting state). Therefore, a driver circuit for GaN HFETs must be able to work under a negative voltage supply VSSH and GND.
Moreover, GaN HFETs operating above 10 MHz demand a high-speed drive circuit with a 50 mA or higher output current. Most of the commercially available PMOS and NMOS transistors have much higher output current rates which are not compatible with GaN HFET devices and lead to unnecessary power loss. In addition, most commercially available power MOSFETs have long rise and fall times. For example, high frequency power MOSFETs have rise and fall times around 10 ns. Using a discrete power PMOS and NMOS as the totem pole pair for the drive circuit will add extra delay to the driver circuit and consequently limit the operation frequency of the drive circuit.
Thus, there is a need for a driver circuit and integrated circuit implementation of a driver circuit that is compatible with GaN HFETs that overcomes the above-mentioned disadvantages.